Processor architecture
US6889317B2 · kind B2 · utility
16Cited by
7References
58Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2001 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | May 1, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An architecture for a pipeline processor circuit, preferably of the VLIW type, comprises a plurality of stages and a network of forwarding paths which connect pairs of said stages, as well as a register file for operand write-back. An optimization-of-power-consumption function is provided via inhibition of writing and subsequent readings in said register file of operands retrievable from said forwarding network on account of their reduced liveness length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.