Flip chip with novel power and ground arrangement
US6890794B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 27, 2004 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | Jan 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a flip chip device comprises providing a semiconductor die having a core area and a periphery area. The periphery area includes an electrostatic discharge (ESD) structure. The semiconductor die including includes at least one power conductor. A substrate having a source of power is provided. A first connection circuit is located within the semiconductor die core area to couple power between the substrate and the semiconductor die power conductor. The ESD structure is electrically coupled to the first connection circuit. The first connection circuit is electrically coupled to the substrate via a conductive bump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.