Semiconductor device having multiple gate oxide layers and method of manufacturing thereof
US6890822B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2003 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | Nov 7, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/981
Abstract
A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region. A second gate oxide overlying the second voltage region and a third gate oxide overlying the third voltage region are formed simultaneously. The second gate oxide is thicker than the third gate oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.