Active matrix substrate and manufacturing method therefor
US6891196B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2003 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | Jul 11, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An active matrix substrate of a channel protection type having a gate electrode, a drain electrode and a pixel electrode is isolated in each layer by insulating films. The active matrix substrate is to be prepared by four masks. A gate electrode layer, a gate insulating film and an a-Si layer are processed to the same shape on a transparent insulating substrate to form a gate electrode layer and a TFF area. A drain electrode layer is formed by a first passivation film with the first passivation film formed as an upper layer. In a second passivation film, formed above the first passivation film, are bored a first opening through the first and second passivation films and a second opening through the second passivation film. A wiring connection layer is formed by ITO provided as an uppermost layer. A storage capacitance unit, including the first and second passivation films sandwiched between the gate electrode and an electrode layer formed as a co-layer with respect to the gate electrode, is connected to the pixel electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.