Metal-insulator-metal capacitor formed by damascene processes between metal interconnect layers and method of forming same
US6891219B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2002 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | Aug 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76838
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Within metal interconnect layers above a substrate of an integrated circuit, a vertical metal-insulator-metal (VMIM) capacitor is formed by the same damascene metallization types of processes that formed the metal interconnect layers. The metal interconnect layers have horizontal metal conductor lines, are vertically separated from other metal interconnect layers by an interlayer dielectric (ILD) layer, and electrically connect to the other metal interconnect layers through via connections extending through the ILD layer. One vertical capacitor plate of the VMIM capacitor is defined by a metal conductor line and a via connection. The other vertical capacitor plate is defined by a metal region adjacent to the metal conductor line and the via connection. The metal conductor line, the via connection and the metal region are formed by the damascene metallization processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.