On-chip PLL locked frequency determination method and system
US6891403B2 · kind B2 · utility
1Cited by
6References
9Claims
0Family size
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Key dates
| Filing date | Oct 22, 2002 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | Feb 5, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2882
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The locked frequency of a PLL is used to latch a test signal through various latching devices (flip-flops or the like). Various different delays are selectively applied to the test signal to provide a delayed test signal and the delayed test signal is measured to determine whether the delay in the test signal matches the jitter in the locked frequency of the PLL. When the delay in the test signal matches the jitter in the locked frequency of the PLL, the respective delay of the test-signal is used to determine the effective locked frequency of the PLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.