Ring oscillator gates in a matrix for aberrant logic gate timing detection
US6891442B2 · kind B2 · utility
17Cited by
8References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2003 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | Jun 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/168
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An array of circuitry forming row and column ring oscillators is provided to determine aberrant gates in an integrated circuit. Control logic is coupled to the rows and columns to enable a ring oscillator of either a row or a column to oscillate. Based on outputs of these oscillations, aberrant gates in an integrated circuit may be more readily studied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.