Calibrating capacitor mismatch in a pipeline ADC
US6891486B1 · kind B1 · utility
16Cited by
5References
43Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2003 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | Nov 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/168
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An on-chip calibration circuit which can dynamically (i.e., in operational environment) measure the capacitor mismatch in an ADC using sampling capacitors to sample an input signal and a feedback capacitor (in combination with an amplifier) for amplification. The measured values can be used to generate accurate digital codes representing analog signal samples. The calibration circuit connects the capacitors to various voltage levels and measures the mismatch levels by examining various signals (e.g., the digital codes) generated in such situations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.