Sigma-delta conversion with analog, nonvolatile trimmed quantized feedback
US6891488B1 · kind B1 · utility
14Cited by
15References
30Claims
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Key dates
| Filing date | Oct 30, 2003 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | Jan 7, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/454
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An Nth-order sigma-delta analog-to-digital converter (ADC) system having multilevel quantized feedback. A multilevel quantized feedback stage incorporates a multibit, current-mode digital-to-analog converter (DAC). In one embodiment, reference current sources for the DAC may comprise a plurality of floating-gate MOS transistors so that analog nonvolatile precision linearity trimming of the feedback DAC may be accomplished. Calibration of the DAC may be performed at a relatively low refresh rate, for example, only at instances when the sigma-delta ADC system is activated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.