Circuit and/or method for implementing a patch mechanism for embedded program ROM
US6891765B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 5, 2003 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | Aug 5, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention concerns an apparatus comprising a memory, a logic circuit and a multiplexer. The memory generally comprises a first address space configured as read only and a second address space configured as read and write. The memory returns a first data item in response to a first address within the first address space. The logic circuit may be configured to (i) deassert a command signal in response to the first address not matching any of a plurality of predetermined addresses and (ii) generate a first branch instruction and assert the command signal in response to the first address matching one of the predetermined addresses in response to the matching. The multiplexer may be configured to select the first data item from the memory or the first branch instruction from the logic circuit in response to the command signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.