Semiconductor memory device and method for pre-charging the same
US6891767B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2003 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | Jun 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device and a method for pre-charging the same, the semiconductor memory device comprising a plurality of memory cell array blocks, each having a plurality of memory cells connected between respective bit line pairs and respective word line pairs, a plurality of pairs of data input/output lines connected to the respective bit line pairs for transferring data, a first pre-charge circuit for pre-charging the bit line pairs to a first pre-charge voltage during a first operation, a second pre-charge circuit for pre-charging the data input/output line pairs and the first pre-charge voltage to the first pre-charge voltage during the first operation, a plurality of third pre-charge circuits, each being disabled in the first operation and pre-charges the data input/output line pairs in the corresponding memory cell array blocks to a second pre-charge voltage during a second operation, and a discharging circuit for lowering the first pre-charge voltage when the first pre-charge voltage is greater than a desired voltage level during the first operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.