Flash/dynamic random access memory field programmable gate array
US6891769B2 · kind B2 · utility
19Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2003 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | Jul 17, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.