Analyzing effectiveness of a computer cache by estimating a hit rate based on applying a subset of real-time addresses to a model of the cache
US6892173B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1998 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | Dec 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for analyzing the effectiveness of a computer cache memory. A bus with memory transactions is monitored. A subset of addresses, along with associated transaction data, on the bus is captured and stored in a memory. The captured addresses are applied to a software model of a computer cache. The capture process is repeated multiple times, each time with a different subset of the address space. Statistical estimates of hit rate and other parameters of interest are computed based on the software model. Multiple cache configurations may be modeled for comparison of performance. Alternatively, a subset of addresses along with associated transaction data is sent to a hardware model of a cache. The contents of the hardware model are periodically dumped to memory or statistical data may be computed and placed in the memory. Statistical estimates of hit rate and other parameters of interest are computed based on the contents of the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.