Hardware semaphores for a multi-processor system within a shared memory architecture
US6892258B1 · kind B1 · utility
1Cited by
16References
21Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 26, 2001 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | Jan 28, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1663
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit generally comprising a memory element and a controller. The memory element may define a semaphore allocatable to a resource. The controller may be configured to (i) present a granted status in response to a processor reading a first address while the semaphore has a free status, (ii) set the semaphore to a busy status in response to presenting the granted status, and (iii) present the busy status in response to the processor reading the first address while the semaphore has the busy status.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.