Method for determining deskew margins in parallel interface receivers
US6892334B2 · kind B2 · utility
3Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2002 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | Nov 7, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0629
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for automatically testing the deskew setting for the clock in a parallel data interface. The deskew value is varied to a high and a low limit to the point where errors occur when transmissions occur. After determining the high and low operable limits of the deskew values, an optimum deskew setting may be determined and set for the system. The present invention may be used as a design verification technique, for optimizing a system after integration, or for further optimization of the deskew value after performing a training pattern for optimizing transmission performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.