Multiple purpose reticle layout for selective printing of test circuits
US6893806B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2002 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | Apr 29, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/44
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for manufacturing a semiconductor wafer uses a reticle having a plurality of spaced apart circuit images of identical patterns or images of a common level of a single integrated circuit formed on the reticle and arranged in columns and rows about its central point. At least one column of spaced apart test images are formed outside of and adjacent an outermost column of circuit images. Radiation is projected through the reticle for exposing the patterns on the reticle onto an underlying wafer. A reticle holder having a pair of shutter elements aligned parallel to the columns of images selectively blocks the projection of radiation through the columns of the test images but are exposed in order to form test circuits on the wafer at selected locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.