Simple process for fabricating semiconductor devices
US6893987B2 · kind B2 · utility
8Cited by
20References
20Claims
0Family size
Assignee
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Key dates
| Filing date | May 7, 2003 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | May 7, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/942
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An alignment pattern is required for photo masks to be exactly aligned with one another; an amorphous silicon is deposited over the entire surface of an insulating layer except for an area where the alignment pattern is to be formed, and a pattern for an ion-implantation and the alignment pattern are concurrently transferred to a photo resist layer; dopant impurity is ion implanted into the amorphous silicon layer by using the photo resist mask, and the insulating layer is selectively etched also by using the photo resist mask; this results in simplification of the process sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.