Single chip ASIC and compact packaging solution for an avalanche photodiode (APD) and bias circuit
US6894266B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2003 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | Nov 15, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A compact integrated APD device integrates the bias voltage and temperature compensation functions inside a standard 4-pin PIN package. The active components of the bias and temperature compensation circuits are integrated into a single ASIC using a high-voltage CMOS process and operated at frequencies of at least 1 MHz to greatly reduce the size of the passive components. To mount the relatively large ASIC chip inside the package with the APD chip, TIA chip and passives, the 4-pin package may be modified by either recessing the pins inside the can to facilitate surface mounting the ASIC or adding a spacer inside the can to facilitate three-dimensional packaging. Communication with the bias and temperature circuits is accomplished using a unique bi-directional 1-wire serial interface via the power supply pin. A clock signal is preferably embedded in the control data to synchronize the APD with an external controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.