Input protection circuit
US6894320B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2002 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | Jan 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/713
Abstract
An input protection circuit is provided which has a high electrostatic discharge (ESD) breakdown voltage and can input a signal in a wide positive and negative voltage range. In a surface layer of a substrate, a well and a field insulating film are formed. An emitter region is formed in the well to form a lateral bipolar transistor having the well as its base. Another emitter region is formed in the surface layer of the substrate to form another lateral bipolar transistor having the well as its collector. A gate electrode layer is formed on the field insulating film between the well and the other emitter region to form a MOS transistor. The emitter region is connected to an input terminal, the well is connected to the gate electrode layer, and the other emitter region and substrate are connected to a ground potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.