Interface for a programmable logic device
US6894531B1 · kind B1 · utility
19Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 22, 2003 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | May 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17744
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides circuitry for implementing a multiple data rate interface architectures for programmable logic devices. The programmable logic device of the invention includes a core and surrounding periphery. The core includes a plurality of logic elements arranged in an array. Some of the logic elements within the core include registers that are used as data registers for the multiple data rate interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.