Pipeline ADC digital dithering for increased digital calibration resolution
US6894631B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2004 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | Mar 31, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/44
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An pipeline analog-to-digital converter (ADC) is provided that is capable of applying calibration at a resolution greater than the resolution of a digital output signal provided by the ADC. The ADC includes a calibration component adapted to apply calibration bits to digital output bits generated by stages of the pipeline and corresponding to samples of an analog input signal. The ADC also includes a random number generator that provides at least one random bit having a sub-LSB bit weight. The calibration bits and the at least one random bit are applied as a dither to the digital output bits such that, on average, the digital output signal provided by the ADC is calibrated at a sub-LSB resolution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.