Liquid crystal display control circuit
US6894673B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2002 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | Nov 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G3/3677
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A liquid crystal display control circuit receives a data enable signal DE in synchronization with per-line based display data from a computer, and thereby controls a liquid crystal display. A gate drive signal outputted from a gate driver 23 is generated according to a vertical clock signal VCK in synchronization with a rise of the signal DE. In order to avoid a variation in the period of charging the pixel electrodes which is caused by a delay in the rise timing of the signal DE and a delay in the signal VCK after the last line, a gate enable signal generation circuit 10 is provided in the liquid crystal display control circuit 1, whereby the extended output of the pulse of the gate drive signal caused by the above-mentioned delays is inhibited. This avoids display inhomogeneity caused by a variation in the data enable signal and the like.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.