Receiver for a memory controller and method thereof
US6895484B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2003 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | Nov 12, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A receiver for a memory controller. The memory controller sends a data request signal to a memory which responds to the data request signal by sending data and a data strobe signal back to the memory controller. The receiver comprises a delay circuit receiving and delaying the data strobe signal, an emulated data strobe signal generator receiving the data request signal to generate an emulated data strobe signal, a push pointer generator generating a plurality of push pointers having priorities, receiving and responding to the emulated data strobe signal by outputting the push pointers in an order according to the priorities, and a buffer receiving and responding to the delayed data strobe signal and the push pointers by storing the data in memory addresses corresponding to the push pointers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.