Stack memory protection
US6895508B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2000 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | Jan 20, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for memory page protection wherein new stack memory load/store instructions are defined for memory management. A corresponding operating system and compiler utilize these new stack memory load/store instructions. Whenever it is desired to have a block of memory used as a stack memory, the stack memory load/store instructions are used. A stack memory attribute is stored in a page table associated with the block of memory. Memory blocks having a stack memory attribute may be read and written into using only stack memory load/store instructions. If a normal load/store is attempted to a memory block having a stack memory attribute a error condition is indicated. Likewise a stack memory load/store to a block of memory not have a stack memory attribute will cause a error condition. Stack memory load/stores meant for one type of stack memory (e.g., program stack attribute) will also cause a fault if the stack load/store is attempted to another type of stack memory (e.g., processor stack). Stack memory (processor stacks), transparent to a programmer writing code for a processor employing stack memory attributes, would have a processor stack attributes assigned by the pr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.