Method of synchronizing operation frequencies of CPU and system RAM in power management process
US6895517B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 16, 2002 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | Sep 30, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A control method of synchronizing operation frequencies of a CPU and a system RAM in a power management process. A power management process is initialized by a system interrupt generated by a power management event. After sending the interrupt control signal output from the chipset to the CPU, the CPU enters a system management mode to execute an interrupt service routine. The interrupt service routine irrelevant to the system RAM configuration is executed first. The shadow RAM control register of the chipset is programmed using the BIOS program to enable the BIOS ROM. A distant jump command is programmed to jump into a predetermined memory address of the BIOS ROM storing a system RAM frequency modulation program to execute the system RAM frequency program. Therefore, the operation frequencies of the CPU and the system RAM are consistent during the power management process to eliminate the instability of system caused thereby.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.