Partitioning integrated circuit hierarchy
US6895562B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2002 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | Dec 7, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus of carrying out a computer assisted analysis function on a hierarchical circuit model. The method is carried out by inputting the hierarchical circuit model, specifying at least one circuit block within the hierarchy as a target of the function on the target block, and simplifying the hierarchical circuit model by deleting circuit blocks not affecting the analysis function, to produce a simplified hierarchical circuit model. A computer assisted analysis function can then be carried out on the simplified hierarchical circuit model. The model is simplified by carrying out a block by block analysis of the hierarchical circuit model to determine if a circuit block is a circuit block desired in the computer assisted analysis and if so keeping the circuit block as part of the simplified hierarchical circuit model; and by carrying out a block by block analysis of the hierarchical circuit model to determine if a circuit block comprises a parent circuit block containing a child circuit block desired in the computer assisted analysis and if so keeping the parent circuit block as part of the simplified hierarchical circuit model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.