Solder terminal and fabricating method thereof
US6897141B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 10, 2004 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | May 10, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3651
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A solder terminal and a fabrication method thereof are provided. According to one embodiment of the present invention, a solder terminal structure includes an adhesion metal layer formed on an electrode pad of a semiconductor device, a thermal diffusion barrier, a solder bonding layer, and a solder bump formed on upper portion of the solder bonding layer. With the thermal diffusion layer, the characteristic deterioration caused by the probe mark generated on the electrode pad can be prevented during a semiconductor reliability test, and at the same time, material movement between the layers of the electrode pad, the solder bonding layer and the adhesion metal layer can be reduced. Also, by having the thermal diffusion barrier act as a solder dam (a layer to confine the melted solder area to prevent the solder from being wetted), an additional deposition or etching process can be omitted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.