Semiconductor device with a capacitor having upper and lower shield layers
US6897509B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2003 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Nov 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The semiconductor device comprises a semiconductor substrate 10; a capacitor element 40 formed above the semiconductor substrate and including a lower electrode 34, a capacitor insulation film 36 formed on the lower electrode and an upper electrode 38 formed on the capacitor insulation film; a shield layer 14; 58 formed at least either of above and below the capacitor element; and a lead-out interconnection layer 22; 50 formed between the capacitor element and the shield layer and electrically connected to the lower electrode or the upper electrode, a plurality of holes 16, 60 being formed in each of the shield layer and the lead-out interconnection layer. The shield layers are formed above and below the MIM capacitor, whereby combination of noises with the MIM capacitor can be prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.