ESD protection circuit
US6897536B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2003 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | May 20, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/603
Abstract
An ESD-protection device includes a gate electrode formed on a substrate; a first diffusion region of a first conductivity type formed in the substrate at a first side of the gate electrode, a second diffusion region of the first conductivity type formed in the substrate at a second side of the gate electrode, and a third diffusion region of a second conductivity type formed in the substrate underneath the second diffusion region in contact with the second diffusion region. Thereby, the impurity concentration level of the third diffusion region is set to be larger than the impurity concentration level of the region of the substrate located at the same depth right underneath the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.