Low drop-out voltage regulator with power supply rejection boost circuit
US6897637B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2002 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Apr 12, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/575
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A low drop-out voltage regulator uses a voltage subtractor circuit 36 to form a power supply rejection boost circuit. The voltage subtractor 36 is inserted between the pass element 20 and the amplifier 26 of the low drop-out regulator. The voltage regulator circuit includes a pass element 20 coupled between an input node and an output node; a voltage feedback circuit 28 and 30 coupled to the output node Vo; an amplifier 26 having an input coupled to the voltage feedback circuit; and a voltage subtractor 36 having a control node coupled to an output of the amplifier 26, an output coupled to a control node of the pass element 20, and an input coupled to the input node. The boost circuit improves supply noise rejection performance significantly without adding much complexity to the regulator system. The boost circuit is simple and consumes negligible silicon area and power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.