Method and integrated circuit for capacitor measurement with digital readout

US6897673B2 · kind B2 · utility

Assignee

• LSI Logic Corporation · US

Inventors

• Scott Savage · Fort Collins, US
• John McNitt · Fort Collins, US
• Sean A. Golliher · Windsor, US

Key dates

• Filing date: Mar 19, 2003
• Grant date: May 24, 2005
• Expiry date: Apr 23, 2023

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R27/2605
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

On-chip absolute value measurement circuit and an on-chip capacitor mismatch value measurement circuits are provided. The absolute value measurement circuit begins charging a capacitor. When the voltage across the capacitor reaches a first threshold, the absolute value measurement circuit starts a counter. When the voltage across the capacitor reaches a second threshold, the counter stops. The counter value is provided as digital output. A computer device reads the digital output and calculates the absolute value of the capacitor based on the counter value. The mismatch measurement circuit repeatedly charges an evaluation capacitor and transfers the charge from the evaluation capacitor to an integrating capacitor. For each transfer of charge, a counter is incremented until the voltage across the integrating capacitor reaches a threshold voltage. The counter value is provided as digital output. This process is repeated for each evaluation capacitor on the chip. A computer device reads each counter value and calculates mismatch values based on the counter values.