Time division multiplexed serial bus with increased bandwidth
US6897681B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 27, 2002 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Mar 27, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The output of drivers which are used to drive the input signals to a multiplexed signal line are combined in a logic OR gate or a logic AND gate prior to connection to the input of the multiplexed line. The inactive state of drivers connected through a logic OR gate is set to 0 and the inactive state of drivers connected through a logic AND gate is set to 1. Bus contention between drivers is eliminated and the bandwidth of the multiplexed serial bus is increased because of the reduced wait time between driver transitions. Power dissipation in transition is reduced and the bus can have a programmable inactive state on a bus to allow for 1, 0 or High Z to indicate the inactive state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.