Phase locked loop with low steady state phase errors and calibration circuit for the same
US6897691B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2003 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | May 15, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (PLL) with low steady state phase errors utilizes a delay unit to delay an input signal or a reference clock so as to lower the steady state phase errors of the PLL. A calibration circuit is used to adjust the delay time of the delay unit and includes a signal generator for generating a simulation input signal and a simulation reference clock according to a phase locked clock; a delay unit for delaying the simulation reference clock and generating a delayed reference clock; a phase detector for detecting the phase error between the simulation input signal and the delayed reference clock and generating charge control signals; a charge pump and an integrator for generating an error voltage according to the charge control signals; a delay time control unit for adjusting the delay time of the delay unit according to the error voltage; and a voltage control oscillator for generating the oscillation clock according to a reference control voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.