Delay locked loop for improving high frequency characteristics and yield
US6897693B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 23, 2001 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Jul 24, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop (DLL) is provided that generates an internal clock signal in synchronization with an external clock signal. First through third amplifiers convert the swing width of the external clock signal to a small swing width and re-convert the external clock signal to an external signal level. A basic clock generator generates a plurality of basic clock signals that are progressively shifted apart by a predetermined phase. First through third duty correctors correct the external clock signal, a first internal clock signal, and a second internal clock signal to satisfy 50% duty. First and second mixers generate a first clock signal and a second clock signal which is 90 degrees out-of-phase with the first clock signal. Finally, the first internal clock signal is 90 degrees out-of-phase with the second internal clock signal. Thus, the first internal clock signal is synchronous with the external clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.