Circuitry for reducing the skew between two signals
US6897694B2 · kind B2 · utility
1Cited by
5References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2003 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Aug 18, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0037
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An electronic integrated circuit includes a first signal (A1) generated by a first source block (10) and a second signal (B1) generated by a second source block (12). A variable delay circuit (18) detects a delay between said first and second signals in calibration mode and applies the delay to the first signal during normal operation of the circuit. A fixed delay buffer (32) may be used to apply a delay to the second signal to compensate for known delays associated with the variable delay circuit (18).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.