Duty-cycle adjustable buffer and method and method for operating same
US6897696B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 29, 2003 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Aug 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A duty-cycle adjustable buffer and a method for operating such buffer can be applied to a clock tree circuit for providing an adjustable duty cycle. The duty-cycle adjustable buffer includes a first inverter and a second inverter connected with each other in series. Each of the first inverter and the second inverter includes a plurality of controlled current charging paths and a plurality of controlled current discharging paths, wherein at least one controlled current charging path and at least one controlled current discharging path of the first inverter and the second inverter are conducted. The timing of the rising edge and falling edge of a clock signal is dynamically adjusted so as to dynamically altering the duty cycle of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.