Amplifier with digital DC offset cancellation feature
US6897700B1 · kind B1 · utility
27Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2003 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Mar 21, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45598
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed, high sensitivity post amplifier as described herein includes a digitally-controlled DC offset cancellation feature. The amplifier circuit is configured to provide DC offset voltage levels in response to a digital control signal, where the digital control signal is generated based upon a data error metric such as bit error rate. The AC signal path and the DC offset adjustment signal path in the amplifier circuit are separated to facilitate operation with normal power supply voltages, and to achieve low power operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.