Method and structure for improving the linearity of MOS switches
US6897701B2 · kind B2 · utility
41Cited by
5References
11Claims
0Family size
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Key dates
| Filing date | May 13, 2003 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | May 13, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/262
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A technique is provided to linearize a MOS switch on-resistance and the nonlinear junction capacitance. The technique linearizes the sampling switch by using a buffer having substantially unity gain with proper DC shift to drive an isolated bulk terminal of the MOS well to improve the spurious free dynamic range (SFDR). In this way, the 2nd-order effect such as nonlinear body effect (VT(VSB)) and nonlinear junction capacitance (Cj(VSB)) can be substantially removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.