Process variation compensated high voltage decoupling capacitor biasing circuit with no DC current
US6897702B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2002 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Jan 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/217
Abstract
Disclosed is a high voltage decoupling capacitor-biasing circuit with no dc current. In one embodiment, the circuit includes a power supply node, a ground node, a common node, a first p-channel FET, a first n-channel FET, and a common node biasing circuit. The first p-channel FET includes a source, gate, and drain, wherein the source and drain of the first p-channel FET are coupled to the power supply node, and wherein the gate of the first p-channel FET is coupled to the common node. The first n-channel FET includes a source, gate, and drain, wherein the source and drain of the first n-channel FET are coupled to the ground node, and wherein the gate of the first n-channel FET is coupled to the common node. The common node biasing circuit is coupled between the power supply and ground nodes. The common node biasing circuit is configured to maintain the common node at a predetermined voltage above ground by charging up or charging down the common node. Further, the common node biasing circuit is configured to transmit only AC current to or from the ground node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.