Floating-gate analog circuit

US6898097B2 · kind B2 · utility

Assignee

• Georgia Tech Research Corporation · US

Inventors

• Jeffery Dugger · Atlanta, US
• Tyson S. Hall · Cleveland, US
• Paul Hasler · Atlanta, US
• David V. Anderson · Alpharetta, US
• Paul D. Smith · Dunlap, US
• Matthew Raymond Kucic · Austell, US
• Abhishek Bandyopadhyay · Winchester, US

Key dates

• Filing date: Mar 24, 2003
• Grant date: May 24, 2005
• Expiry date: Jun 25, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03F2203/45121
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

In one exemplary embodiment, a programmable analog array (PAA) contains a configurable analog matrix having two floating-gate field effect transistors (FETs). Also contained in the PAA is an interconnect circuit that is programmable to configure the configurable analog matrix to operate in one or more of several matrix modes. A few examples of such matrix modes include a switching matrix mode, a memory matrix mode, and a computing matrix mode. In an exemplary method of configuring the PAA. PAA, the the method includes programming an interconnection, for example, between a first terminal of the first floating-gate FET and a first terminal of the second floating-gate FET. The method further includes programming an interconnection, for example, between a gate terminal of the first floating-gate FET and a fixed voltage source, for setting a floating gate charge on the first floating-gate FET.