Scheme for maintaining synchronization in an inherently asynchronous system
US6898211B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 1999 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Jun 16, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0697
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A synchronization state for a local clock generating circuit of a first of a number of components of a distributed system is maintained according to a number of local clock cycles recorded between successive occurrences of a global synchronization signal provided to the components within the distributed system. The local clock generating circuit may enters the synchronization state only after observing a predetermined number of occurrences of successive local clock cycles between instances of the global synchronization signal. The local clock generating circuit continues to provide local control signals for the first of the components at time instants corresponding to the number of local clock cycles even after an instance of the global synchronization signal is observed at a time instant corresponding to one local clock cycle more or less than the number of local clock cycles. However, the local clock generating circuit enters an alarm state when the global synchronization signal is observed at time instants corresponding to more than one local clock cycle more or less than the number of local clock cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.