Apparatus, method, and system for synchronizing information prefetch between processors and memory controllers
US6898674B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2002 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Jun 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment of the invention, a prefetcher in a memory controller is described which includes logic to receive memory request hints from a CPU. The memory request hints are used by the prefetcher in the memory controller to prefetch information from one or more memory devices coupled to the memory controller via a memory bus. The prefetcher in the memory controller further includes logic to determine the types of memory request hints provided by the CPU, the types of memory request hints are used to indicate whether the hints provided by the CPU are for instruction memory read request or data memory read request. The prefetcher in the memory controller also includes logic to generate prefetch requests to prefetch information from the one or more memory devices, based on the types of memory request hints provided by the CPU and bandwidth availability of the memory bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.