Hardware loops
US6898693B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 2, 2000 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Oct 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/325
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a programmable processor is adapted to include loop hardware to increase processing speed without significantly increasing power consumption. During a first pass through a loop, a first subset of a sequence of instructions may be loaded into the loop hardware. Then, during subsequent passes through the loop the first subset may be issued from the loop hardware while a second subset is retrieved from a memory device. In this manner, the second subset may be issued with no additional penalty after the first subset has been issued.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.