Clock generation systems and methods
US6898721B2 · kind B2 · utility
32Cited by
14References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 22, 2001 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | May 16, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; a wireless transceiver transmitting and receiving at a frequency based on a wireless clock input; and a controller having a plurality of clock outputs each coupled to the clock inputs of the processing units and the wireless clock input, the clock outputs being generated from a common master clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.