Auto quiesce
US6898732B1 · kind B1 · utility
8Cited by
13References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2001 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Dec 5, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing device having multiple masters. The device includes a set of masters and at least one target with at least one bus that provides connecting between the masters and the target. A system controller operates to quiesce masters selected from the set of masters in response to an error message. A system error processor handles the error condition after the selected masters have been quiesced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.