Split and merge design flow concept for fast turnaround time of circuit layout design

US6898770B2 · kind B2 · utility

Assignee

• LSI Logic Corporation · US

Inventors

• Human Boluki · Munich, DE
• Benjamin Mbouombouo · San Jose, US
• Johann Leyrer · Munich, DE

Key dates

• Filing date: Jan 9, 2003
• Grant date: May 24, 2005
• Expiry date: Jul 1, 2023

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/3312
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method and system is disclosed to improve the turnaround time to provide adequate time to meet project schedules in the event that adjustments or modifications to the design are necessary. A method for improving a turnaround time for design verification of a process database representing a semiconductor design includes the steps of (a) deriving a timing database and a (DNE) database from the process database; (b) performing, using the timing database, one or more design changes and one or more timing verifications and corrections to generate a modified timing database; (c) initiating, using the process database, physical validation of the semiconductor design prior to completion of step (b) to generate a modified DNE database; (d) merging the modified timing database with the modified DNE database to form a modified process database; and (e) performing, using the modified process database, one or more design verification checks of the semiconductor design.