Semiconductor device and its manufacture method

US6900088B2 · kind B2 · utility

Assignee

• FUJITSU LIMITED · JP

Inventors

• Ryota Nanjo · Kawasaki, JP
• Shinji Sugatani · Saitama, JP
• Satoshi Nakai · Osaka, JP

Key dates

• Filing date: Feb 28, 2002
• Grant date: May 31, 2005
• Expiry date: Feb 28, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

First and second gate electrodes are formed on first and second regions of a semiconductor substrate. Second conductivity type impurities are implanted into the second region to form first impurity diffusion regions. Spacer films are formed on the side surfaces of the first and second gate electrodes. Second conductivity type impurities are implanted into the first and second regions to form second impurity diffusion regions. After the spacer films are removed, second conductivity type impurities are implanted into the first region to form third impurity diffusion regions. The third activation process is performed so that the gradient of impurity concentration distribution around the third impurity diffusion region becomes steeper than the gradient of impurity concentration distribution around the first impurity diffusion region.