Method of testing an integrated circuit and an integrated circuit test apparatus
US6900656B1 · kind B1 · utility
6Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2003 |
| Grant date | May 31, 2005 |
| Priority date | — |
| Expiry date | Nov 26, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of testing an Integrated Circuit (IC) and an IC test apparatus is provided. In one embodiment, the method of testing includes (1) applying a voltage to the IC that is not a normal operating voltage of the IC and (2) temporarily biasing a well voltage of transistors in the IC allowing screening for the normal operating voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.