Apparatus and method for generating a predetermined time delay in a semiconductor circuit
US6900683B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2000 |
| Grant date | May 31, 2005 |
| Priority date | — |
| Expiry date | Dec 5, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0688
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor arrangement is provided for generating a predetermined time delay. Two clocks are connected to two parallel, redundant semi-conductor circuits emitting clock signals from multiplexers. The redundant circuits receive delayed clock signals from one of the clocks, and from the other clock, clock signals that are delayed in adjustable delay circuits to be phased in with the clock signals from the first clock. A number of delay elements and a first reference number of delay elements, providing a predetermined delay time, are connected in a reference delay circuit. A quotient of the two numbers is stored. One of the semi-conductor circuits is replaced by an alternative semi-conductor circuit, the reference delay circuit of which is set on the predetermined delay time, corresponding to a second reference number of delay elements. An adjustable delay circuit is set on the same delay time as the replaced semi-conductor circuit by means of the second reference number and the quotient.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.