Method for rasterizing graphics for optimal tiling performance
US6900803B2 · kind B2 · utility
5Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2002 |
| Grant date | May 31, 2005 |
| Priority date | — |
| Expiry date | Apr 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T11/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphics system and method are disclosed that may optimize the rate of pixel generation to match the rate at which a memory may be designed to receive pixel data. If a memory is configured to store multiple pixels substantially simultaneously, it may be advantageous to render an equivalent number of pixels substantially simultaneously and at the same rate. An edge walker that utilizes multiple sets of accumulators to generate multiple scan lines substantially simultaneously and a span walker that utilizes multiple sets of accumulators to render multiple pixel values substantially simultaneously is described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.